1. Field of the Invention
This invention relates to a semiconductor device that has a so-called superjunction structure and a method for manufacturing the semiconductor device.
2. Description of Related Art
An attempt has been carried out to enhance the withstand voltage of semiconductor devices provided with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
FIG. 4 is a diagrammatic sectional view of a conventional semiconductor device provided with MOSFETs.
A semiconductor layer 54 including an N-type drift layer (N-type pillar layer) 52 and a P-type resurf layer (P-type pillar layer) 53 is formed on an N++-type semiconductor substrate 51. The drift layer 52 and the resurf layer 53 are alternately arranged in a direction parallel to the semiconductor substrate 51, thus forming a so-called superjunction structure.
A plurality of trenches 55 are formed. Each of the trenches 55 has a depth so as to penetrate through the semiconductor layer 54 in its thickness direction, and reach an interface between the semiconductor substrate 51 and the semiconductor layer 54. The trenches 55 each have their inner side walls almost perpendicular to the semiconductor substrate 51, and are almost evenly spaced in parallel with each other. The inner side wall of the trench 55 is covered with an oxide film 63, and the inside thereof is filled with a buried layer 64 made of polysilicon or dielectric material.
The drift layer 52 is disposed along the trench 55. The resurf layer 53 is disposed between a pair of drift layers 52 that are respectively disposed along the inner side walls of two adjoining trenches 55.
An N-type region 56 is formed on the drift layer 52. A P-type base region 57 is formed on the resurf layer 53 in such a way as to come into contact with the N-type region 56. An N-type source region 58 is formed on the surface part of the base region 57.
A gate electrode 60 is disposed so as to face the base region 57 placed between the N-type region 56 and the source region 58 and so as to face the vicinity thereof, with an insulating film 59 therebetween. A source electrode 61 is electrically connected to the source region 58 and the base region 57. A drain electrode 62 is formed on a rear surface of the semiconductor substrate 51 (i.e., on a surface opposite to the surface on which the gate electrode 60 and the source electrode 61 are formed).
This semiconductor device is used in a state in which one of the source electrode 61 and the drain electrode 62 is connected to an external load and in a state in which a fixed voltage is applied between the external load and the other one of the source electrode 61 and the drain electrode 62 by means of a power source. The voltage applied therebetween gives a reverse bias to a PN junction formed between the resurf layer 53 and the drift layer 52.
In the base region 57 between the N-type region 56 and the source region 58, a channel is formed near the interface between the base region 57 and the insulating film 59 by setting the gate electrode 60 at a suitable electric potential in this state. Further, reverse bias divided by the external load and by the on-resistance of the MOSFET is applied onto the PN junction formed between the resurf layer 53 and the drift layer 52. However, a depletion layer generated by this is only slightly spread, and a path for carriers (electrons) is left in the drift layer 52.
As a result, an electric current flows from the drain electrode 62 to the source electrode 61 through the semiconductor substrate 51, the drift layer 52, the N-type region 56, the vicinity (channel) of the interface between the base region 57 and the insulating film 59, and the source region 58. This semiconductor device has a so-called planar-type structure, and an electric current flows in a direction parallel to the semiconductor substrate 51 near the channel.
Next, a description will be given of a situation in which the MOSFET is in an OFF-state, i.e., a situation in which the gate electrode 60 is not set at the suitable electric potential mentioned above and no channel is formed. Since an electric current does not flow to the MOSFET in this situation, the power-supply voltage is directly applied onto the PN junction formed between the drift layer 52 and the resurf layer 53 as reverse bias. Therefore, a depletion layer is swiftly spread from the interface S between the drift layer 52 and the resurf layer 53 to the drift layer 52 and the resurf layer 53, so that the drift layer 52 and the resurf layer 53 are completely depleted. Hence, the on-resistance can be reduced by doping the drift layer 52 with impurities at a high concentration, and excellent withstand voltage characteristics (e.g., 200V) can be additionally obtained.
In a process for manufacturing the semiconductor device, the drift layer 52 is formed by injecting impurities to the inner wall surface of the trench 55. The trench 55 has been used only to form the drift layer 52, and has not been effectively used.
The thus structured semiconductor device is disclosed by Japanese Published Unexamined Patent Application No. 2003-46082.
However, the planar-type semiconductor device has difficulty in miniaturizing elements, and, for this reason, regions where channels are formed cannot be enlarged for each unit area. Therefore, in practice, the on-resistance cannot be much lowered.